IS210BPPCH1AEC | I/O Pack processor board |SR489-P5-LO-A20-E | IS430SNUAH1A

Model: IS210BPPCH1AEC

Category: I/O Pack processor board

Delivery method: SF Express/Federal

Remittance: Wire transfer/Western Union

Control power supply: nominal 25 VA, maximum 35 VA

Insulation voltage: 300 volts

Communication protocol: Modbus RTU or DNP 3.0

Data record storage: 2 to 16 events with 2048 to 256 data samples

Waveform capture sampling rate: 16 per cycle

Product description

The IS210BPPCH1AEC is an I/O Pack processor board designed for use with Mark VIe systems. Mark VIe’s I/O packet is labeled H1B. The BPPC board is an upgraded version of the earlier BPPB I/O package for systems with ControlST V04.04 or later. These are not security packages and are not designed for use on the Mark VIeS system. However, in TMR (Triple Modular Redundancy) systems, BPPC boards can be used with earlier BPPB-based I/O packages.

Main features and functions:

Core components: The IS210BPPCH1AEC processor board is the core of the dSPACE standard component system, which extends various I/O boards through internal high-speed buses (such as PHS bus) to meet the needs of users for I/O.

Hardware core: The embedded CPU is the hardware core of the processor board, and its model selection determines the performance of the entire system. For example, the DS1005.PPC processor board uses Motorola’s PowerPC750 processor and has a main frequency of 480MHz.

Communication capability: The IS210BPPCH1AEC processor board communicates with the PC host through Ethernet, and has a standard communication interface, which can communicate with the computer to achieve data transmission and sharing.

Function expansion: The processor board can be extended through the dedicated processor interface to form a parallel multi-processor system, which greatly speeds up the simulation speed of the model and ADAPTS to the user’s requirements for fast and real-time computing models.

Data processing: The IS210BPPCH1AEC processor board has enough data storage space to save test result data in offline test mode.

Test and control: The processor board has an embedded CPU independent of the calculation to realize the operation and control of the test process, and the CPU can work in the state of waiting to download the program and the test mode.